Design of the elastic buffer size for SDH equipments

Abstract

In the SDH frame structure, a large amount of non-information bits and the pointer adjustment mechanism make the design of the buffer size more complicated compared with that of the PDH. The paper analyzes the buffer operation in the pointer processor, and gives the proper buffer size for different phase detection methods. The paper also analyzes the main elements that influence the buffer size of the desynchronizer (demultiplexer). These analyses are useful for the design of the buffer size in SDH equipment.