An Improved Clock Cycle Measurement Method for High-Speed Serial Signal with Duty-Cycle-Distortion Jitter

Abstract

Software clock data recovery (CDR) is a critical component of a high-speed serial link that recovers the reference clock from a serial signal, which are generally used in real-time sampling oscilloscopes and electronic design automation software. The common method for calculating the period of the reference clock is to extract the rising and falling edges of the signal, and then calculate the difference between adjacent transition edges, so that a pulse width sequence is obtained. By performing statistics on this sequence, it can be found that the value of the position of the first peak of the statistical histogram is the period of the reference clock, the position of the second peak is twice the period of the clock, etc. The period of the clock can be calculated by weighted average. However, high-speed serial signals inevitably have duty-cycle-distortion (DCD) jitter, and DCD seriously affect the determination of the position of the peak of the above statistical histogram, there are many spurious peaks near the actual peak. This article proposes an improved method of calculating the clock period, which can eliminate the influence of DCD and to obtain an accurate clock period.