Improved effective capacitance computations for use in logic and layout optimization

Abstract

We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach makes it suitable for the analysis loop within performance-driven iterative layout optimization. We present an iterationless approach for computing the effective capacitance of an interconnect load at a gate output when the slew time is non-zero (i.e., a ramp). We then extend this effective capacitance algorithm to complex gates, i.e., channel-connected components. Preliminary experimental results using the new effective capacitance approach show that the resulting delay estimates are quite accurate-within 15% of HSPICE-computed delays on data taken from a recent microprocessor design in 0.25 /spl mu/m CMOS technology. The improved driver model reduces the cell delay calculation errors to below 10%; this indicates that accurate modeling of effective capacitance is no longer the dominant source of errors in cell delay calculation.