Frontend model generation for SAT-based property checking

Abstract

This paper provides an overview on recently developed model generation techniques for SAT-based property checking. To overcome limitations of SAT-based property checking, we suggest to tailor synthesis procedures in the frontend of the property checker towards the verification algorithms used in the backend. This paradigm has been applied to two different design categories. As a first example, for control intensive designs with many interacting state machines, appropriate state encoding can facilitate the representation of state sets. As a second example, for arithmetic datapath verification, we suggest to synthesize an arithmetic bit level description to enable normalization techniques in the backend. We demonstrate the usefulness of our approach by means of industrial test cases.