Design of Ratioless Ternary Inverter Using Graphene Barristor

Abstract

This study proposes a design of a ternary logic inverter using graphene barristor (GB). To design a multiple-valued logic gate, controlling threshold voltages of the unit device should be easy. We determined that the doping concentration of the graphene can easily control the operation voltage of the GB. To realize an ideal ternary logic gate, the concept of a single pole triple throw switch is proposed and designed using the GB. The designed ratioless GB ternary inverter was simulated using SPICE and Mathematica. Voltage transfer characteristics of the proposed ternary inverter showed sharp ternary characteristics and its static power consumption was nearly zero.