Decoupling Capacitor Optimization for Flat $\mathrm{Z}$ PCB Power Distribution Networks

H. Barnes, S. Sandler
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Abstract

Power integrity applications suffer from the inability to precisely define the dynamic transient current. This has led to an increased interest in designing for a target impedance over a wide spectral bandwidth. Prior art has shown that a flat impedance design results in the lowest m V ripple excursion per Amp of step load. [1] This paper provides a simple method for estimating the required decoupling C for flat impedance. This method is then used to demonstrate the adverse effect of inductance in the PDN that requires an increase in the required total decoupling capacitance.
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平$\ mathm {Z}$ PCB配电网的去耦电容优化
功率完整性应用无法精确定义动态瞬态电流。这导致了在宽频谱带宽上设计目标阻抗的兴趣增加。现有技术表明,平坦阻抗设计导致每安培阶跃负载的最小毫伏纹波偏移。[1]本文提供了一种估算平坦阻抗所需去耦C的简单方法。然后使用该方法来演示PDN中电感的不利影响,该电感需要增加所需的总去耦电容。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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