Pipelined Implementations for Belief Propagation Polar Decoder: From Formula to Hardware

Abstract

A general design method for pipelined belief propagation (BP) polar decoder is proposed in this paper. By associating data flow graph (DFG) of polar encoder with factor graph (FG) of BP polar decoder, regular structure of FG helps to determine the generation formula representing pipelined BP polar decoder. Using Python as a compiler, the generation formula is translated into a series of synthesizable Verilog HDL files for various code lengths and parallelisms. Considering the balance between performance and cost, this formula-to-hardware design can be extended to explore the design space, where we are able to make tradeoffs according to specific application requirements. With the evaluation of auto-generation system, implementation results have shown that our design is reliable and practicable.