Low-power CDMA multiuser receiver architectures

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI:10.1109/SIPS.1999.822355

Tao Long, Naresh R Shanbhag

引用次数: 15

Abstract

Presented in this paper are low-power, reconfigurable adaptive CDMA multiuser receiver architectures developed via dynamic algorithmic transforms (DAT). The architectures achieve low-power operation via run-time reconfiguration of receiver complexity to match the requirements of a time-varying multiuser channel. Simulation results with 0.25 /spl mu/m, 2.3 V CMOS technology parameters indicate that the proposed architectures have high resistance to the near-far problem, and can achieve up to 60.4% in power savings compared to architectures without DAT depending on the interference situation.

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低功耗CDMA多用户接收机结构

本文提出了基于动态算法变换(DAT)的低功耗、可重构自适应CDMA多用户接收机架构。该体系结构通过运行时重新配置接收器复杂度来满足时变多用户信道的要求，从而实现低功耗操作。在0.25 /spl mu/m, 2.3 V CMOS技术参数下的仿真结果表明，所提出的架构具有很高的抗近远问题能力，并且根据不同的干扰情况，与无DAT的架构相比，可实现高达60.4%的功耗节约。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

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