Virtual channel router architecture for Network on Chip with adaptive inter-port buffers sharing

Abstract

Network on chip (NoC) is the new efficient interconnection structure of nowadays complex system on chips. The performance of NoC in terms of latency, throughput and power consumption should be optimized. Since buffers consume around 60% area and 30% power of the whole router, the relationship between network performance and memory resources has to be considered. In this paper, we propose a new router architecture enabling an adaptive virtual channels sharing among different input ports. This router solves the problem of virtual channels underutilization; it improves the area and power consumption performance without affecting the latency.