Pulse-position and pulse-amplitude modulation interface for serial data link applications

Waleed Madany, M. Rashdan, E. Hasaneen
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引用次数: 5

Abstract

A serial communication link based on pulse-amplitude modulation combined with pulse-position modulation is presented in this paper. The timing problem that occurs when combining the pulse-position modulation and the pulse-amplitude modulation has been resolved using the proposed technique by applying the AM modulation to the data signal and the clock signal. Using the proposed architecture, the reception of the pulse-position modulated bits will not be affected by the combining of the amplitude modulation and the number of the amplitude levels can be increased as many as possible. The PPM technique and the AM technique are combined in so as to increase the total number of the transmitted bits without affecting the transmitted data signal bandwidth. A 5 bits 4 GB/s PAM-PPM link has been designed and simulated in 130 nm CMOS technology using 800 MHz input clock signal. The simulation results indicate that combining PAM technique with PPM technique increases the number of transmitted bits per clock cycle of the data signal without altering the bandwidth. The simulated power consumption of the designed transceiver is less than 90mW.
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用于串行数据链路应用的脉冲位置和脉冲幅度调制接口
提出了一种基于脉冲幅度调制和脉冲位置调制相结合的串行通信链路。通过对数据信号和时钟信号进行调幅调制,解决了脉冲位置调制和脉冲幅度调制相结合时出现的时序问题。利用所提出的结构,脉冲位置调制比特的接收不会受到幅度调制组合的影响,并且幅度电平的数量可以尽可能多地增加。将PPM技术和AM技术相结合,在不影响传输数据信号带宽的情况下增加了传输比特的总数。在130 nm CMOS技术下设计并仿真了一个5位4gb /s的PAM-PPM链路,输入时钟信号为800 MHz。仿真结果表明,将PAM技术与PPM技术相结合,在不改变带宽的前提下,提高了数据信号每个时钟周期的传输位数。所设计收发器的仿真功耗小于90mW。
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