A scalable architecture for discrete wavelet transform

S. B. Syed, M. Bayoumi
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引用次数: 14

Abstract

We present the design and prototyping of an efficient systolic architecture which performs both forward and inverse discrete wavelet transform. The proposed architecture consists of a linear array of processing elements, each of which has an adder and a multiplier and fixed number of I/O channels. The wavelet transform is computed by convolution and by mapping the computation on to a linear array of systolic processing elements. The design of the architecture has been shown to be simple, scalable and has the advantage of low I/O bandwidth. The number of processing elements is independent of the size of the input. The architecture has been prototyped using 2/spl mu/m p-well CMOS technology and has been developed in the CADENCE Edge Design Framework environment.
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离散小波变换的可扩展结构
我们提出了一种高效的收缩结构的设计和原型,它可以同时进行正、逆离散小波变换。所提出的架构由线性阵列的处理元件组成,每个处理元件都有一个加法器和一个乘法器以及固定数量的I/O通道。小波变换是通过卷积和将计算映射到收缩处理元素的线性阵列来计算的。该体系结构的设计简单、可扩展,并且具有低I/O带宽的优点。处理元素的数量与输入的大小无关。该架构采用2/spl mu/m p-well CMOS技术进行原型设计,并在CADENCE边缘设计框架环境中开发。
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