High linearity 2-bit current steering InP/GaInAs DHBT digital-to-analog converter

Abstract

We present a high linearity 2-bit digital-to-analog converter (DAC) implemented in an InP/GaInAs DHBT technology. The DAC is based upon the current steering architecture. Cascode structure and layout techniques, i.e. static shuffling and dummy devices, have been used to enhance the linearity. The DAC exhibits static integral/differential nonlinearities of 5.5×10−3 LSB, equivalent to a resolution of 9.2 bits. Dynamic measurements qualitatively show proper behavior at 6 GS/s, while simulations with typical on-chip load exhibit sufficiently fast settling at 20 GS/s.