A programmable digital neuro-processor design with dynamically reconfigurable pipeline/parallel architecture

Abstract

Previous neural network processors were configured either into a SIMD or into an instruction systolic array (ISA) ring architecture using the canonical mapping methodology. The disadvantages of these processors are the lack of generality, scalability, programmability and reconfigurability. So, we propose a programmable neuroprocessor whose architecture is dynamically reconfigurable into either SIMD or an ISA ring according to the data dependencies of any neural network model. To improve the computing time, the computation of an activation function, which typically needed tens of cycles in previous processors, can be done in a single cycle by using piecewise linear (PWL) function approximation. Using a simple bus architecture and instruction set, the proposed processor allows the implementation of neural networks larger than the physical processor element array and allows the user to solve any neural network model. We verify these properties with the error backpropagation (EBP) model and estimate the computation time of the proposed processor.