Jung-Soo Choi, Ji-Yong Yoo, Seung-won Lim, Young-Seok Kim
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引用次数: 60
Abstract
The dead time in PWM inverters is generally used to avoid the short circuit of the DC source. Even though the dead time is chosen to be just a few microseconds, the adverse effects of that on an entire cycle of the inverter output voltage cause serious problems such as waveform distortion and voltage drop. In this paper, a novel dead time minimization algorithm is proposed for improving the inverter output performance. The proposed algorithm consists of forbidding unnecessary triggers for the inverter switches that are not turned on although the gate drive signal is triggered. The validity of the proposed method is verified by comparing the simulation and experimental results with those of the conventional methods. It is concluded from the results that the proposed algorithm can reduce the output current harmonics and the number of inverter switchings.
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