Implementation of a highly scalable blokus duo solver on FPGA

Abstract

This paper presents a highly scalable hardware solver for Blokus Duo. Based on flat Monte Carlo method, the proposed solver contains self-contained agents whose number is configurable and only limited by FPGA capacity, which makes the proposed solver highly scalable. Data structures and tile representations are tailored to support efficient memory usage and operations. Implementation result shows that an agent can operate at up to 150MHz while requiring less than 3000 LUTs on the Altera Cyclone II EP2C70F896C6 FPGA device. Simulation result shows the proposed solver can always win level 1 Pentobi.