Research of local dynamics of the phase-locked loop

Y. Gelozhe, P. Klimenko, A. Maksimov
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引用次数: 1

Abstract

Measures to reduce the influence of the dead zone of frequency-sensitive phase detector on frequency deviation of the signal generated by the phase-locked loop (PLL) the circuit of which includes the binomial low-pass filter of the fifth order, providing additional ripple suppression of control voltage are defined here. With the help of simulation method of Matlab program it was shown 60°...70° that to reduce the peak frequency deviation it is necessary to ensure the stability margin of the automatic system at phase. Given stability margin from 26° to 80° systematic frequency shift of the generated signal is observed, despite the fact that the system under consideration has astatism of the second order.
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锁相环局部动力学研究
本文定义了降低频率敏感鉴相器死区对锁相环(PLL)产生的信号频率偏差影响的措施,锁相环的电路包括五阶二项低通滤波器,提供额外的控制电压纹波抑制。借助Matlab程序的仿真方法,实现了60°…70°,为了减小峰值频率偏差,必须保证自动系统的相位稳定裕度。给定从26°到80°的稳定裕度,可以观察到所产生信号的系统频移,尽管所考虑的系统具有二阶失稳性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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