An Empirical Analysis of the Fidelity of VPR Area Models

Abstract

This work provides an empirical analysis on the fidelity of the VPR area models. Both the original minimum width transistor area model and the new COFFE model are compared against actual layouts with up to 3 metal layers of the various FPGA building blocks. We found that both models have significant variations with respect to the actual layout area. Most importantly both models offer relatively low fidelity in layout area estimation with the widely used original VPR model overestimates layout area of larger buffers and full adders by as much as 22%-34% while underestimates the layout area of smaller buffers and multiplexers by as much as -43%. The newer COFFE model also significantly overestimates the layout area of a full adder by 13% and underestimates the layout area of multiplexers by -55% to -30%. Such a variation is particularly significant considering many previous architectural studies based on these models have differentiated architectures based on the area or area delay product variations as low as a few percentage points. Our results suggest that the actual layout area must be used to achieve a highly accurate FPGA area model.