Secure systolic architecture for montgomery modular multiplication algorithm

Abstract

A novel secure architecture of secure systolic Montgomery modular multiplier resilient to Fault-Injection attacks is proposed. The proposed architecture has been verified by modeling, implementing and testing it using VHDL. The error mask probability is under 0.0015% when we set the check integer properly. The performances of proposed architecture are comparable to those of other schemes in literature, where the hardware overheads vary from 5.68% to 46.44% in different types of implementations, and the time overheads are close to 0.