Low-error and area-efficient fixed-width multiplier by using minor input correction vector

Abstract

In this paper, we propose a new error compensation circuit by using dual group minor input correction vector to lower compensation error. By utilizing the symmetric property of MIC and construct the error compensation circuit mainly by the “outer” partial products, the hardware complexity can be lowered and only increases slightly as the multiplier input bits increase. In the proposed 16-bit fixed-width multiplier, the truncation error can be reduced by 87% as compared with the direct-truncated multiplier and the transistor counts can be reduced by 47% as compared with the full-length multiplier.