Layout optimization by pattern modification

Abstract

A new and practical approach to several layout optimization problems is introduced. A novel two-dimensional pattern generator, in connection with a set of routing and placement transformations, is employed to efficiently solve problems ranging from wire crossing minimization and topological via minimization to minimum Steiner tree optimization and IO alignment. The expected running time is O(n log n) and the space requirement is O(n), where n is the number of layout objects. The system was fully coded and tested, and excellent results in both laboratory and real-life examples were achieved.<>