Design of a Low-Cost Approximate Adder with a Zero Truncation

Abstract

We propose a cost-effective approximate adder using a zero truncation technique with acceptable accuracy. The proposed adder design reduces the area by up to 23% compared to the approximate adders considered in this paper when implemented with a 32-nm CMOS technology. Furthermore, our adder shows 16%, 10%, 10%, and 16% better performance in area, power, power-delay product, and area-delay product, respectively, than the lower-part OR adder while providing an acceptable accuracy performance. To see the impact of approximation errors caused by our adder on real applications, it is adopted in a digital image processing and demonstrates that our adder rarely affects the output image quality.