Impact of technology on low-voltage CMOS and BiCMOS switching delay

K.L. Davis, J. Yuan
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Abstract

An alternative switching delay reduction technique for CMOS and BiCMOS digital circuits is examined. A simplified BSIM3V2 model equation is used to analyze CMOS inverter delay for different V/sub DD/, T/sub ox/, and V/sub T/. PSPICE BiCMOS delay results are presented over a wide range of V/sub DD/, T/sub ox/, and V/sub T/.
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技术对低压CMOS和BiCMOS开关延迟的影响
研究了一种用于CMOS和BiCMOS数字电路的替代开关延迟降低技术。采用简化的BSIM3V2模型方程分析了不同V/sub DD/、T/sub ox/和V/sub T/下的CMOS逆变器延迟。PSPICE BiCMOS在V/sub DD/、T/sub ox/和V/sub T/宽范围内的延迟结果。
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