Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, A. Elshazly, P. Hanumolu
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引用次数: 6
Abstract
A digital fractional-N PLL that employs a time amplifier based TDC and a truly fractional divider to achieve low in-band noise with a wide bandwidth of 3MHz is presented. Fabricated in 65nm CMOS process, the prototype PLL consumes 3.7mW at 4.5GHz output frequency and achieves better than -106dBc/Hz in-band noise and 490fsrms integrated jitter. This translates to a FoMJ of -240.5dB, which is the best among the reported fractional-N PLLs.
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