M. Kumazawa, N. Tokunaga, H. Senda, T. Ishii, T. Fukuoka
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引用次数: 0
Abstract
A single chip consisting of a 256/64 QAM demodulator, a VSB demodulator, a FEC decoder, and a QPSK demodulator is described. To reduce area, we adopted a complete shared architecture of the equalizer regarding the VSB/QAM demodulator, and accomplished the entire byte operation of MPEG frame formatting regarding the FEC decoder, which realized thirty percent reduction.
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