Charge Analysis in SAR ADC with Discrete-Time Reference Driver

Abstract

This paper provides detailed mathematical analysis that investigate the effect of charge-sharing between an analog-to-digital converter (ADC) reference decoupling capacitor and a charge-redistribution based differential split-monotonic capacitive digital-to-analog converter (CDAC). A discrete-time reference driver is used to charge the decoupling capacitor in the sampling phase, forming a closed-system in the hold phase which allows us to apply a charge-based analysis to determine the voltages at several nodes within the system such as the reference capacitors and comparator inputs. The generalized mathematical model can be used to accurately determine the voltage shift on the comparator inputs and hence quantify the effect on the SAR comparator decision level with a varying reference decoupling capacitor which can ultimately be used to optimize the size of the capacitor while maintaining high SNDR/SFDR. In this design, we utilize a differential decoupling capacitor which provides a 4x capacitor area decrease compared to its single ended counterparts.