Design of Low Power Multiplier using CNTFET

2017 IEEE 7th International Advance Computing Conference (IACC) Pub Date : 1900-01-01 DOI:10.1109/IACC.2017.0120

Rajendra Prasad Somineni, S. Jaweed

引用次数: 5

Abstract

Multiplication is an essential vital role in arithmetic operations. In fact, multiplication is allotted on operations like Multiply and Accumulate (MAC). The exaggerate form of Braun multiplier is the Baugh-Wooley multiplier. This work proposes the design of Low-power Baugh-Wooley Multiplier with CMOS full adder with different topologies like 10T, 14T, 17T as well as with CNTFET full adders using different topologies like 10T, 14T, 17T. All circuits are designed and simulated using HSPICE Tool.

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基于CNTFET的低功率倍增器设计

乘法在算术运算中起着至关重要的作用。实际上，乘法是在乘法和累加(MAC)等操作上分配的。布劳恩乘数的夸张形式是鲍威乘数。本工作提出了采用不同拓扑结构(如10T、14T、17T)的CMOS全加法器以及采用不同拓扑结构(如10T、14T、17T)的CNTFET全加法器的低功耗Baugh-Wooley乘法器的设计。使用HSPICE工具对所有电路进行了设计和仿真。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2017 IEEE 7th International Advance Computing Conference (IACC)

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