{"title":"Circuit design techniques for deep submicron technologies","authors":"S. Rusu","doi":"10.1109/TUTCAS.2001.946982","DOIUrl":null,"url":null,"abstract":"This article presents design techniques for deep submicron integrated circuits. It includes a discussion of both chip-level design challenges (capacitive and inductive noise, domino vs. static design styles, dual V/sub T/ transistors and clock distribution) and system-level design challenges.","PeriodicalId":376181,"journal":{"name":"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TUTCAS.2001.946982","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This article presents design techniques for deep submicron integrated circuits. It includes a discussion of both chip-level design challenges (capacitive and inductive noise, domino vs. static design styles, dual V/sub T/ transistors and clock distribution) and system-level design challenges.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
