Design and Analysis of VCO in PLL System

Xiu-long Wu, Jun-ning Chen, Meng Jian
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Abstract

A wide-bandwidth low-noise VCO used in PLL system was investigated, including a harmonic filtering resistor and source damping resistors to reduce the phase noise and power dissipation. The back-to-back varactor topology is identified as a suitable solution to linearize the tank capacitance. The amplitude to phase noise conversion is greatly attenuated. The circuit was simulated using 0.35um CMOS technology in Mentor Graphics Eldo-RF environment, the simulation results show that the phase noise of the oscillator can reach -119.5dBc/Hz@1MHz, the power dissipation is 3.0mw at 2.4GHz.
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锁相环系统中压控振荡器的设计与分析
研究了一种用于锁相环系统的宽带低噪声压控振荡器,包括谐波滤波电阻和源阻尼电阻,以降低相位噪声和功耗。背靠背变容管拓扑被认为是一种合适的解决方案来线性化油箱电容。幅相噪声转换得到了极大的衰减。采用0.35um CMOS技术在Mentor Graphics Eldo-RF环境下对电路进行仿真,仿真结果表明,该振荡器的相位噪声可达-119.5dBc/Hz@1MHz, 2.4GHz时功耗为3.0mw。
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