Hardware implementation of the Temporal Noise Shaping decoder for DAB+ baseband chip

Hongsheng Zhang, Guoyu Wang, Mingying Lu, Renyi Zhu
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Abstract

Advanced Audio Coding (AAC) is adopted by the Digital Audio Broadcasting plus (DAB+) system, which is the upgraded version of DAB. The increasing demand of the portable DAB+ receivers requires low-cost, low-power DAB+ baseband chip. This brings the demand of hardware-architecture AAC decoders. This paper reports a hardware implementation of the Temporal Noise Shaping (TNS) decoder, which is an important tool in AAC to eliminate the pre-echo phenomenon. The proposed TNS decoder shares the process unit with other AAC blocks to save silicon area, and uses gated clock to reduce power consumption. The design consumes only 516 logic elements and 64*18 bits ROM. It has been integrated in a DAB+ baseband chip and works well for several DAB+ receivers.
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用于DAB+基带芯片的时序噪声整形解码器的硬件实现
数字音频广播+ (Digital Audio Broadcasting plus, DAB+)系统采用高级音频编码(Advanced Audio Coding, AAC)技术,是DAB的升级版。便携式DAB+接收机的需求日益增长,需要低成本、低功耗的DAB+基带芯片。这就对AAC解码器的硬件架构提出了要求。本文报道了时域噪声整形(TNS)解码器的硬件实现,它是AAC中消除预回波现象的重要工具。本文提出的TNS解码器与其他AAC模块共享处理单元以节省硅面积,并使用门控时钟以降低功耗。该设计仅消耗516个逻辑元件和64*18位ROM,集成在DAB+基带芯片中,适用于多种DAB+接收机。
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