Energy and power issues in Network-on Chip

Abstract

The Network-on-Chip (NoC) has emerged as an essential infrastructure for design of any complex System-on-Chip. The NoC provides efficient technique to exchange the data between different domains of Intellectual property (IP) cores. This also provides paradigm for integrating large number Intellectual Property (IP). Due to ever increasing integration of IPs the need of Network-on-Chip for efficient communication is essential. The power associated with the NoC is to be dealt because majority of the power is dissipated due to interconnection. In this paper we have investigated various levels where power can be reduced. This paper also presents mathematical model that can be applied to reduce the power.