A Design of ID Sorting Module Based on Quick Sorting Algorithm

Haonan Tang, Shuqin Geng, Xiaohong Peng, Shuaiqi Yan, Yan Zhang, Zifeng Wang
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Abstract

Based on the quick sorting algorithm, this paper uses verilog language to implement the RTL design of the ID sorting module applied to the CAN bus controller, and performs functional simulation on the module. Simulation results show that the ID sorting module designed in this paper can quickly sort up to 64 different ID numbers and output correct sequence to meet the design requirements. Using a parametric design strategy, the ID sorting module designed in this paper can configure parameters to achieve the function of sorting a larger number of random sequences to meet different needs, and has high scalability and practicality.
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基于快速排序算法的ID排序模块设计
基于快速排序算法,采用verilog语言实现了应用于CAN总线控制器的ID排序模块的RTL设计,并对该模块进行了功能仿真。仿真结果表明,本文设计的ID排序模块可以快速对多达64个不同的ID号进行排序,并输出正确的顺序,满足设计要求。本文设计的ID排序模块采用参数化设计策略,可以通过配置参数实现对大量随机序列进行排序的功能,满足不同需求,具有较高的可扩展性和实用性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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