L. Knoll, A. Schafer, S. Trellenkamp, K. Bourdelle, Q. Zhao, S. Mantl
{"title":"Nanowire and planar UTB SOI Schottky Barrier MOSFETs with dopant segregation","authors":"L. Knoll, A. Schafer, S. Trellenkamp, K. Bourdelle, Q. Zhao, S. Mantl","doi":"10.1109/ULIS.2012.6193353","DOIUrl":null,"url":null,"abstract":"Schottky Barrier MOSFETs were fabricated on ultra thin body (UTB) SOI with planar and NW-array device geometry. Implantation into Silicide (IIS) was used to lower the Schottky Barrier height for n- and p-type MOSFETs. The enhanced gate control of the NW array reduces Drain Induced Barrier Lowering (DIBL) and improves the subthreshold slope in n-type MOSFETs, whereas the corrected current drops. In p-type MOSFETs on current and Ion/Ioff ratio is enhanced.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ULIS.2012.6193353","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
Schottky Barrier MOSFETs were fabricated on ultra thin body (UTB) SOI with planar and NW-array device geometry. Implantation into Silicide (IIS) was used to lower the Schottky Barrier height for n- and p-type MOSFETs. The enhanced gate control of the NW array reduces Drain Induced Barrier Lowering (DIBL) and improves the subthreshold slope in n-type MOSFETs, whereas the corrected current drops. In p-type MOSFETs on current and Ion/Ioff ratio is enhanced.