Universal guideline for CMOS I/O signal integrity

Abstract

BERT measurements have been used to characterize the digital receiver sensitivity during asynchronous ground bounce events and provide a reference point to establish a guideline for ground bounce criteria. Simultaneously switched digitally controlled output buffers improve the signal integrity of receivers over seven orders of magnitude when compared to conventional buffers. An algorithm with strong support of measurements has been used to develop a graphical approach to predicting the required power lead count of a packaged CMOS device.