A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip

Abstract

A reconfigurable on-die Traffic Generator (TG) is proposed to test the packet switched 2D-mesh network of a 48 iA-32 core Single-chip Cloud Computer. The Single-chip Cloud Computer (SCC) is an experimental processor created by Intel Labs. The 24-tile Network-on-Chip (NoC) consists of a Traffic Generator per tile which can be programmed to generate deterministic and random traffic patterns. It also consists of reconfigurable activity control, (non)-cacheable reads and writes, message class and route control bits to feed synthetic traffic to the network to investigate NoC functional, protocol issues and to measure the key power-performance metrics. In this paper, we present the architecture and design details of the Traffic Generator, operating modes, re-configurability and the testing procedures. This semi-custom design has a transistor count of 54K, which is 0.1% of tile transistor count, and occupies 0.3mm2 area which is 0.9% of tile area. The estimated power consumption is only 23mW at 1.1V and at 500C, 0.02% of the total chip power in 45nm high-K nine metal CMOS process.