Achieving flexibility in a Viterbi decoder DSP coprocessor

Abstract

A Viterbi decoder hardware implementation suitable for wireless cellular applications is presented. This decoder is extremely flexible, both in the codes it handles, and in its system interface. Capabilities include multiple constraint lengths, multiple code rates, arbitrary frame size, puncturing and code polynomials. This paper discusses aspects of the implementation for which achieving this flexibility proved to be difficult. With a data throughput rate of 2.5 Mbps it is an ideal solution for 3rd generation base station architectures operating in conjunction with a DSP.