Rebuilding synthesized design hierarchy based on instances path names of flattened netlist

Abstract

Hierarchical representation can greatly simplify many FPGA Computer-Aided Design (CAD) operations such as: design verification, partitioning and placement. In this paper, we propose a hierarchical synthesis environment for Mesh-based FPGA architectures. Our proposed approach uses the flattened netlist resulting from ODIN II tool and reconstructs the hierarchy of the initial Verilog design according to instances names. Results show that reconstructing design hierarchy enables to reduce the number of external nets compared with flattened netlist.