A high throughput configurable parallel encoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes

Abstract

In this paper, we are proposing a new architecture for fast encoding of Quasi-Cyclic Low-Density Parity Codes (QC-LDPC). QC-LDPC codes are becoming more and more popular in a wide range of applications, including data transmission (WiMAX, DVB-S2) in telecommunication systems, increasing the need for effective encoder architectures. In our approach, support for a large subset of QC-LDPC codes is provided thanks to the configurability of the architecture at synthesis level. High levels of parallelism can be reached, and hence high throughput achieved, due to the modular encoder architecture that takes advantage of the highly regular structure of QC-LDPC parity check matrices. The architectural design has been validated through implementation on an Altera Stratix II FPGA of different encoders related to DVB-T2 and DVB-S2. Very high data rates (up to 28.9 GB/s) have been achieved with still acceptable hardware consumption (about 32k logic elements) proving the effectiveness of the approach.