Restructuring the flow of image and video processing programs to increase instruction level parallelism

Abstract

This paper addresses the problem of preparing efficient implementations of Image Processing (IP) tasks for Instruction Level Parallel (ILP, i.e., superscalar and pipelined) architectures. First it shows an accurate analysis of ILP architectures and IP task structures. This analysis allows identifying specific sources of inefficiency that affect typical implementations of IP programs for ILP architectures. Then, it introduces a novel processing model, named Bucket Processing (BP), aimed at reducing the inefficiencies of IP programs characterized by the presence of nested loops, typical of image processing, and by the presence of conditional statements in the innermost loop bodies. Finally, it describes how BP restructures the program flow in such a way to deliver significant speed up in programs running on real ILP platforms.