A Fast Accurate Interpretive Simulator Based on Shared Basic Block Cache Technique

Abstract

Instruction set simulator plays a very important role in new micro-architecture design domain and cross-platform software design and development. The simulation speed performance and the simulation accuracy are the two most important factors that are used to evaluate simulators. Interpretive instruction simulation technique and compiled instruction simulation technique are the most common used and mature simulation technique. Interpretive instruction simulation technique is flexible and accurate, however, due to its simulation mechanism it has a slow simulation speed. In this paper, a new fast accurate interpretive simulator based on shared basic block cache technique is proposed, which takes advantages of the temporal and spatial locality principle to extremely improve the efficiency of time-consuming fetch-decoding phases of interpretive simulation technique. And the experimental tests show that the shared basic block interpretive simulation technique is especially superior to handle large target machine applications due it mechanism.