Design and FPGA implementation of ternary hardware IP core for square root function

Abstract

This paper presents an algorithm of ternary hardware IP core and its implementation on FPGA. This IP core that solves the square root function is considered as the first developed algorithm that handles a complex ternary mathematical operation. The algorithm has been coded using VHDL language, simulated and implemented using Xilinx Spartan 3 FPGA board. Design results have proven not only accurate results that our IP code provides (error equals 0) but also its good performance in terms of latency, FPGA resources and power consumption.