Design and characterization of a 65nm CMOS wireless RFID reader for ECoG tag

Abstract

A SpV-resolution RFID ECoG data reader bas been designed and implemented in 65nm CMOS TSMC technology. The area occupancy is 1.8mm×l.9mm. In this paper, the design and measurement results are shown. The circuit average power consumption is less than 36μW for the analog part while the peak power of the digital one is 19mW (including the output buffers and protections) with supply of 1.2V, providing power transmission 300MHz by a class Ε PA. The data coming from 1MHz from the tag modulates the AC power and the envelope detector allow the acquisition. The asynchronous demodulation achieves a BER less than 10−6. The novelty of the solution and the experimental measurements propose the architecture as a pioneer for the ECoG reading out architecture.