A Programmable Spread Spectrum Clock Generation

2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI:10.1109/ICASIC.2007.4415635

J. Zheng, P. Ren, C. C. Shao, Yi Yang, Juncheng Wang, Wei Li, Chinglong Lin, Yuhua Cheng, Yangyuan Wang

引用次数: 2

Abstract

In this paper, a spread-spectrum clock generator (SSCG) with triangular modulation is presented. The proposed SSCG with a third-order sigma-delta modulator can generate clocks with center spread ratios of 0.25%, 1%, 1.75%, 2.5%, 3.5%, 5% and down spread ratios of 0.5%, 2%, 3.5%, 5%, 7%, 10%. The SSCG is implemented on a chip using SMIC 0.13 um CMOS process. Measurements show that 11.31 dB attenuation of the EMI at 80 MHz with down spread ratio of 10% and 12.98 dB attenuation at 133.3 M with center spread ratio of 5% can be achieved which have a good agreement with the theoretical calculations.

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一个可编程扩频时钟发生器

提出了一种三角形调制扩频时钟发生器(SSCG)。采用三阶σ - δ调制器的SSCG可以产生中心扩展比为0.25%、1%、1.75%、2.5%、3.5%、5%和下扩展比为0.5%、2%、3.5%、5%、7%、10%的时钟。SSCG采用中芯0.13 um CMOS工艺在芯片上实现。测量结果表明，在80 MHz和133.3 M频段，下展比分别为10%和12.98 dB, EMI的衰减与理论计算结果吻合较好。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2007 7th International Conference on ASIC

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