E. Gonauser, W. Braeckelmann, K. Delker, K. Schoen, W. Wilhelm, A. Glasl
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引用次数: 0
Abstract
A 36.6 mm2 masterslice array with 58 fully TTL-compatible I/O-ports is described. The chip features 1ns internal gate delay, a power dissipation of 0.6 mW per gate and a single 5 V supply.
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