{"title":"A 2MHz-Bandwidth 11.6-bit ENOB Noise-shaping SAR ADC with 2nd Order Passive Integrator","authors":"Haoran Weng, Weilin Xu","doi":"10.1109/ICICM50929.2020.9292155","DOIUrl":null,"url":null,"abstract":"Instead of active noise-shaping with power hungry amplifiers, a 2nd order passive noise-shaping module with 8-bit asynchronous successive approximation register (SAR) ADC is presented in this paper. This 2nd order passive noise-shaping module only composes of 4 switches and 4 capacitors, which is benefit for chip area saving. In addition, only one noise-shaping module is needed in differential signal processing, while traditional design needs two modules. The three-input comparator has been optimized to decrease kick-back noise. Simulation results show that the ADC achieves 11.6-bit ENOB with 2MHz signal bandwidth and 80MS/s sampling-rate in 45nm CMOS process, and power consumption is 300uW.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICM50929.2020.9292155","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Instead of active noise-shaping with power hungry amplifiers, a 2nd order passive noise-shaping module with 8-bit asynchronous successive approximation register (SAR) ADC is presented in this paper. This 2nd order passive noise-shaping module only composes of 4 switches and 4 capacitors, which is benefit for chip area saving. In addition, only one noise-shaping module is needed in differential signal processing, while traditional design needs two modules. The three-input comparator has been optimized to decrease kick-back noise. Simulation results show that the ADC achieves 11.6-bit ENOB with 2MHz signal bandwidth and 80MS/s sampling-rate in 45nm CMOS process, and power consumption is 300uW.
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