A 1.2 V micropower CMOS op amp with floating-gate input transistors

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI:10.1109/MWSCAS.2000.952875

E. Raisanen-Ruotsalainen, K. Lasanen, J. Kostamovaara

引用次数: 29

Abstract

A micropower 1.2 V op amp has been integrated in a 0.35 /spl mu/m CMOS process. Floating-gate input transistors are used to increase the input common mode voltage range of the op amp. Measured dc gain of the op amp is 65 dB. With a 9 pF load unity gain bandwidth is 230 kHz and phase margin is 62/spl deg/. Input referred noise is 0.5 /spl mu/V//spl radic/(Hz) at 10 Hz and 0.15 /spl mu/V/(Hz) at 10 kHz. Current consumption of the op amp is 4.3 /spl mu/A and active area is 0.11 mm/sup 2/.

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带有浮栅输入晶体管的1.2 V微功率CMOS运放

在0.35 /spl mu/m CMOS工艺中集成了一个微功率1.2 V运放。采用浮栅输入晶体管增加运放的输入共模电压范围，运放的实测直流增益为65 dB。在9 pF负载下，单位增益带宽为230 kHz，相位裕度为62/spl度/。输入参考噪声在10hz时为0.5 /spl mu/V//spl径向/(Hz)，在10khz时为0.15 /spl mu/V/(Hz)。运算放大器的电流消耗为4.3 /spl mu/A，有源面积为0.11 mm/sup 2/。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)

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