Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

Abstract

In this paper a high performance signal stepping based multimode multi-threshold CMOS technique is introduced which reduces standby leakage current and provides a better way to control the ground bounce noise during sleep to active mode transition using one additional mode i.e. wait mode. Analysis of signal stepping based multimode multi-threshold CMOS technique using low power 16-bit full adder has been done for reduction of standby leakage current and ground bounce noise. Further, to see the effectiveness of signal stepping based multimode multi-threshold CMOS technique, simulation has been done for low power 16 bit full adder in BPTM 90nm technology with supply voltage of 1V at room temperature. Results show that this technique reduces ground bounce noise by 95.80 % and standby leakage current by 19.24% as compared to the standard trimode MTCMOS technique.