Towards a common RT-level subset of VHDL

Abstract

Summary form only given. The activities and goals of the European working group on synthesis requirements for VHSIC hardware description language (VHDL) are described. Some of the problems concerning the use of VHDL at RT level are reported. A formal model for hardware semantics of RT-level VHDL could rely on deterministic automata. This is important for the cooperation of synthesis and formal verification methods.<>