Fast design space exploration framework with an efficient performance estimation technique

Abstract

This work presents the design space exploration framework that consists of two design loops: cosynthesis loop for component selection and mapping of the function blocks to the processing components, and communication DSE loop for communication architecture optimization. Before entering into the cosynthesis loop, it is critical to estimate the performance of junction blocks. We also propose a performance estimation method of software function blocks considering the effect of architecture variation, compiler optimization, and data dependent behavior. It is to run the entire application with code augmentation on the instruction set simulator of the target processor. In the cosynthesis loop, the performance of the entire application is easily computed as a linear combination Of function block performance values. Experimentation with real-life applications proves the viability of the proposed technique.