Comprehensive Evaluation of Packet Flow Control Methods for a Ring Nework of Processors on Chip

Abstract

A Current design of a system-on-chip (SoC) technology is constructing under increasing demand for high performance, small size and energy-efficient design. To fulfill these demands, it is required to consider a suitable design for on chip interconnection network. In this paper, we design a prototype of communications unit (CU) for a network-on-chip (NoC) architecture based on ring processors interconnection whose structure is simple to provide a SoC model with small size, low-cost and low energy consumption solutions for designing SoC system. Three types of packet flow control methods, such as, store-and-forward (SF), virtual cut-through (VCT) and wormhole routing (WH) have been implemented and compared in view of designing a hardware-efficient SoC architecture. Furthermore, computer based simulations with a clock cycle level of a CPU in the CU were preformed and transmission latency, throughput, and capability for load balancing were analyzed and compared. From the results that have been obtained show that VCT gives better performances, while SF and WH are more economical in memory consumption for short and long packet length, respectively.