{"title":"Dual use of power lines for data communications in microprocessors","authors":"V. Chawla, D. Ha","doi":"10.1109/DDECS.2011.5783041","DOIUrl":null,"url":null,"abstract":"We proposed power line communication (PLC) through a microprocessor's power distribution network as a novel technique for communicating to any node inside a chip and demonstrated the suitability of Impulse Ultra-Wideband (UWB) communication. Applications of this scheme discussed in this paper exemplify the applicability of this scheme in future microprocessors. Further, data recovery block design is presented which detects short duration UWB impulses on its power line. The design has been done in IBM 0.13 um digital CMOS process and has been shown to consume 3.58 mW when operating from 1.2 V supply.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2011.5783041","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
We proposed power line communication (PLC) through a microprocessor's power distribution network as a novel technique for communicating to any node inside a chip and demonstrated the suitability of Impulse Ultra-Wideband (UWB) communication. Applications of this scheme discussed in this paper exemplify the applicability of this scheme in future microprocessors. Further, data recovery block design is presented which detects short duration UWB impulses on its power line. The design has been done in IBM 0.13 um digital CMOS process and has been shown to consume 3.58 mW when operating from 1.2 V supply.
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